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one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a bipolar/jfet, audio operational amplifier op176* features low noise: 6 nv/ ? hz high slew rate: 25 v/ m s wide bandwidth: 10 mhz low supply current: 2.5 ma low offset voltage: 1 mv unity gain stable so-8 package applications line driver active filters fast amplifiers integrators pin connections 8-lead narrow-body so 8-lead epoxy dip (s suffix) (p suffix) null ?n +in v? nc v+ out null 1 2 3 45 6 7 8 op176 1 2 3 45 6 7 8 null ?n +in v? op-482 nc v+ out null op176 general description the op176 is a low noise, high output drive op amp that features the butler amplifier front-end. this new front-end design combines both bipolar and jfet transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of jfets. total harmonic distortion plus noise equals previous audio amplifiers, but at much lower supply currents. improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. input offset voltage is guaranteed at 1 mv and is typically less than 200 m v. this allows the op176 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. the output is capable of driving 600 w loads to 10 v rms while maintaining low distortion. thd + noise at 3 v rms is a low 0.0006%. the op176 is specified over the extended industrial (C40 c to +85 c) temperature range. op176s are available in both plastic dip and so-8 packages. so-8 packages are available in 2500 piece reels. many audio amplifiers are not offered in so-8 surface mount packages for a variety of reasons, however, the op176 was designed so that it would offer full performance in surface mount packaging. *protected by u.s. patent no. 5101126. simplified schematic rb4 rb3 qb5 rb5 qb6 rb7 rb6 qb7 j1 r4 q9 q10 j2 q2 q1 z2 q6 q5 ccb cf qs1 rs1 r5 6 rs2 qs2 r3 q3 q4 qs3 qb9 q8 q11 q7 cc2 4 qb8 r2l r2p1 r2a r2p2 r2s 5 r1p2 1 r1p1 r1l r1a r1s qb3 z1 qb1 jb1 qb4 cb1 qb2 rb1 rb2 cc1 3 2 7
electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 1mv offset voltage v os C40 c t a +85 c 1.25 mv input bias current i b v cm = 0 v 350 na v cm = 0 v, C40 c t a +85 c 400 na input offset current i os v cm = 0 v 50 na v cm = 0 v, C40 c t a +85 c 100 na input voltage range v cm C10.5 +10.5 v common-mode rejection cmrr v cm = 10.5 v, C40 c t a +85 c 80 106 db large signal voltage gain a vo r l = 2 k w 250 v/mv r l = 2 k w , C40 c t a +85 c 175 v/mv r l = 600 w 200 v/mv offset voltage drift d v os / d t5 m v/ c output characteristics output voltage swing v o r l = 2 k w , C40 c t a +85 c C13.5 +13.5 v r l = 600 w , v s = 18 v C14.8 +14.8 v output short circuit current i sc 25 50 ma power supply power supply rejection ratio psrr v s = 4.5 v to 18 v 86 108 db C40 c t a +85 c80 db supply current i sy v s = 4.5 v to 18 v, v o = 0 v, r l = , C40 c t a +85 c 2.5 ma supply current i sy v s = 22 v, v o = 0 v, r l = , C40 c t a +85 c 2.75 ma supply voltage range v s 4.5 22 v dynamic performance slew rate sr r l = 2 k w 15 25 v/ m s gain bandwidth product gbp 10 mhz audio performance thd + noise v in = 3 v rms, r l = 2 k w , f = 1 khz 0.001 % voltage noise density e n f = 1 khz 6 nv/ ? hz current noise density i n f = 1 khz 0.5 pa/ ? hz specifications subject to change without notice. rev. 0 C2C op176Cspecifications (@ v s = 15.0 v, t a = +25 c unless otherwise noted)
op176 rev. 0 C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . 7.5 v output short-circuit duration to gnd . . . . . . . . . . indefinite storage temperature range p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range op176g . . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c package type q ja 3 q jc units 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for input voltages greater than 7.5 v limit input current to less than 5 ma. 3 q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for p-dip packages; q ja is specified for device soldered in circuit board for soic package. (@ v s = 15.0 v, t a = +25 c unless otherwise noted) warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the op176 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. parameter symbol conditions limit units offset voltage v os 1 mv max input bias current i b v cm = 0 v 350 na max input offset current i os v cm = 0 v 50 na max input voltage range 1 v cm 10.5 v min common-mode rejection cmrr v cm = 10.5 v 80 db min power supply rejection ratio psrr v = 4.5 v to 18 v 86 db min large signal voltage gain a vo r l = 2 k w 250 v/mv min output voltage range v o r l = 2 k w 13.5 v min v s = 18.0 v, r l = 600 w 14.8 v min supply current i sy v s = 22.0 v, v o = 0 v, r l = 2.75 ma max v s = 4.5 v to 18 v, 2.5 ma max v o = 0 v, r l = notes electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 guaranteed by cmr test. op176 die size 0.069 0.067 inch, 4,623 sq. mils. substrate (die backside) is connected to vC. transistor count, 26. wafer test limits null v + out null ?n +in v dice characteristics ordering guide model temperature range package description package option op176gp C40 c to +85 c 8-pin plastic dip n-8 op176gs C40 c to +85 c 8-pin soic so-8 op176gsr C40 c to +85 c so-8 reel, 2500 pieces op176gbc +25 c dice
figure 3. input bias current vs. temperature figure 6. supply current per amplifier vs. supply voltage op176Ctypical characteristics rev. 0 C4C figure 1. input offset voltage drift distribution @ 15 v figure 4. maximum output swing vs. frequency figure 2. output swing vs. temperature figure 5. maximum output swing vs. load resistance 120 0 8 60 20 1 40 0 100 80 7 5 4 36 2 m t c v os ? m v/? aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa v s = 15v ?0? t a +85? based on 300 op amps 16 8 0 10 100 10k 1k 4 12 14 10 6 2 w load resistance ? w output swing ?volts positive swing negative swing v s = 15v t a = +25? 2.50 1.50 0 25 2.25 1.75 5 2.00 15 20 10 supply voltage ?v supply current ?ma t a = +85? t a = +25? t a = ?0? 16 12 100 13 ?5 ?0 14 15 75 50 25 0 temperature ?? absolute output voltage ?v w v s = 18v, +v om , r l = 600 w w v s = 15v, +v om , r l = 600 w w v s = 15v, +v om , r l = 2k w w v s = 18v, ? ? om ? , r l = 600 w w v s = 15v, ? ? om ? , r l = 2k w w v s = 15v, ? ? om ? , r l = 600 w 30 15 0 10k 10m 1m 100k 1k 10 5 20 25 v s = 15v w t a = +25? frequency ?hz maximum output swing ?volts r l = 2k 300 0 100 150 50 ?5 100 ?0 250 200 75 50 25 0 temperature ?? input bias current ?na v s = 15v v cm = 0v
op176 rev. 0 C5C figure 10. power supply rejection vs. frequency figure 7. short circuit current vs. temperature @ 15 v figure 8. open-loop gain & phase vs. frequency figure 11. open-loop gain vs. temperature figure 12. closed-loop output impedance vs. frequency figure 9. closed-loop gain vs. frequency 120 60 0 1k 1m 100k 10k 100 40 20 80 100 frequency ?hz power supply rejection ?db v s = 15v t a = +25? +psrr ?srr frequency ?hz gain ?db 120 100 ?0 1k 10k 100m 10m 1m 100k 80 60 40 20 0 ?0 ?0 gain phase phase margin = 60 90 135 180 225 phase ?degrees t a = +25? v s = 15v r l = >600 w 50 10 ?0 1k 10k 100m 10m 1m 100k 20 30 40 ?0 ?0 0 frequency ?hz gain ?db t a = +25? v s = 15v 2000 0 100 500 250 ?5 ?0 1000 750 1250 1500 1750 75 50 25 0 temperature ?? open-loop gain ?v/mv v s = 15v v o = 10v w ?ain, r l = 2k w +gain, r l = 600 w ?ain, r l = 600 w +gain, r l = 2k w 40 20 0 1k 1m 100k 10k 100 10 30 frequency ?hz w impedance ? w a v = +100 a v = +10 a v = +1 t a = +25? v s = 15v 80 0 100 20 10 ?5 ?0 40 30 50 60 70 75 50 25 0 temperature ?? absolute output current ?ma sink source v s = 15v
op176 rev. 0 C6C figure 16. gain bandwidth product & phase margin vs. temperature figure 13. common-mode rejection vs. frequency figure 14. small signal overshoot vs. load capacitance figure 17. slew rate vs. load capacitance figure 18. slew rate vs. temperature figure 15. slew rate vs. differential input voltage 65 45 ?5 125 60 50 ?0 55 75 100 50 25 0 ?5 v s = 15v 14 6 12 8 10 temperature ?? phase margin ?degrees gain bandwidth product ?mhz phase gain 50 0 2000 30 10 200 20 0 40 1800 1600 1400 1200 1000 800 600 400 load capacitance ?pf slew rate ?v/s negative slew rate positive slew rate v s = 15v r l = 2k w swing = 10v slew window = 5v t a = +25? 140 100 0 1k 1m 100k 10k 100 120 60 80 20 40 frerquency ?hz common-mode rejection ?db t a = +25? v s = 15v 100 0 1000 30 10 100 20 0 60 40 50 70 80 90 900 800 700 600 500 400 300 200 v s = 15v load capacitance ?pf overshoot ?% negative swing positive swing w r l = 2k w v in = 100mvp-p av cl = 1 40 0 100 10 5 ?5 ?0 20 15 25 30 35 75 50 25 0 v s = 15v w r l = 2k w slew rate ?v/? temperature ?? sr sr+ 35 0 2.0 15 5 0.4 10 0 30 20 25 1.6 1.2 0.8 slew rate ?v/s differential input voltage ?v sr+ and sr w v s = 15v r l = 2k w t a = +25?
op176 rev. 0 C7C figure 22. large signal transient response 25 20 0 10 100 10k 1k 15 10 5 v s = 15v w t a = +25? frequency ?hz voltage noise ?nv/ hz figure 21. current noise density vs. frequency figure 19. voltage noise density vs. frequency 10k 2.5 2.0 0 10 100 1k 1.5 1.0 0.5 frequency ?hz current noise ?pa/ hz v s = 15v t a = +25? figure 20. small signal transient response time ?500ns/div v out (5v/div) 10 90 100 0% 5v 500ns aaaaa aaaaa aaaaa aaaaa aa aa aa aa aa aa aaaaa aaaaa aaaaa aa aa aa aa aa aa aaaaa aaaaa aaaaa aa aa aa aa aa aa v out (50mv/div) time ?00ns/div 10 90 100 0% 50mv 100ns
op176 rev. 0 C8C applications short circuit protection the op176 has been designed with output short circuit protection. the typical output drive current is 50 ma. this high output current and wide output swing combine to yield an excellent audio amplifier, even when driving large signals, at low power and in a small package. total harmonic distortion total harmonic distortion + noise (thd + n) of the op176 is well below 0.001% with any load down to 600 w . however, this is dependent upon the peak output swing. in figure 23 it is seen that the thd + noise with 3 v rms output is below 0.001%. in the following figure 24, thd + noise is below 0.001% for the 10 k w and 2 k w loads but increases to above 0.01% for the 600 w load condition. this is a result of the output swing capability of the op176. notice the results in figure 25, showing thd vs. v in (v rms). figure 23. thd + noise vs. frequency 0.1 0.010 0.001 0.0001 20 100 1k 10k 20k v s = 18v v o = 10vrms w 600 w 2k w 10k w figure 24. thd + noise vs. r load figure 25. thd + noise vs. output amplitude (v rms) the output of the op176 is designed to maintain low harmonic distortion while driving 600 w loads. however, driving 600 w loads with very high output swings results in higher distortion if clipping occurs. to attain low harmonic distortion with large output swings, supply voltages may be increased. figure 26 shows the perfor- mance of the op176 driving 600 w loads with supply voltages varying from 18 volts to 20 volts. notice that with 18 volt supplies the distortion is fairly high, while with 20 volt supplies it is a very low 0.0007%. 0.1 0.010 0.001 0.0001 20 100 1k 10k 20k w r l = 600 w v o = 18v v o = 20v v o = 19v v o = 22v figure 26. thd + noise vs. supply voltage v s = 15v v o = 3vrms 0.1 0.010 0.001 .0001 20 100 1k 10k 20k w 600 w 0.1 0.010 0.001 .0001 20 100 1k 10k 20k v s = 18v w r l = 600 w w 10vrms w 5vrms w 3vrms w 1vrms
op176 rev. 0 C9C noise the voltage noise density of the op176 is below 6 nv/ ? hz from 30 hz. this enables low noise designs to have good perfor- mance throughout the full audio range. figure 27 shows a typical op176 with a 1/f corner at 6 hz. figure 27. 1/f noise corner noise testing for audio applications the noise density is usually the most important noise parameter. for characterization the op176 is tested using an audio precision, system one. the input signal to the audio precision must be amplified enough to measure accurately. for the op176 the noise is gained by approximately 1020 using the circuit shown in figure 28. any readings on the audio precision must then be divided by the gain. in imple- menting this test fixture, good supply bypassing is essential. figure 28. noise test upgrading 5534 sockets the op176 is a superior amplifier for upgrading existing designs using the industry standard 5534. in most application circuits, the op176 can directly replace the 5534 without any modifications to the surrounding circuitry. like the 5534, the op176 follows the industry standard, single op amp pinout. the difference between these two devices is the location of the null pins and the 5534s compensation capacitor. the 5534 normally requires a 22 pf capacitor between pins 5 and 8 for stable operation. since the op176 is internally compensated for unity gain operation, it does not require external compensation. nevertheless, if the 5534 socket already includes a capacitor, the op176 can be inserted without removing it. since the op176s pin 8 is a no connect pin, there is no internal connection to that pin. thus, the 22 pf capacitor would be electrically connected through pin 5 to the internal nulling circuitry. with the other end left open, the capacitor should have no effect on the circuit. however, to avoid altogether any possibility for noise injection, it is recom- mended that the 22 pf capacitor be cut out of the circuit entirely. if the original 5534 socket includes offset nulling circuitry, one would find a 10 k w to 100 k w potentiometer connected between pins 1 and 8 with said potentiometers wiper arm connected to v+. in order to upgrade the socket to the op176, this circuit should be removed before inserting the op176 for its offset nulling scheme uses pins 1 and 5. whereas the wiper arm of the 5534 trimming potentiometer is connected to the positive supply, the op176s wiper arm is connected to the negative supply. directly substituting the op176 into the original socket would inject a large current imbalance into its input stage. in this case, the potentiometer should be removed altogether, or, if nulling is still required, the trimming potentiometer should be rewired to match the nulling circuit as illustrated in figure 29. figure 29. offset voltage nulling scheme input overcurrent protection the maximum input differential voltage that can be applied to the op176 is determined by a pair of internal zener diodes connected across its inputs. they limit the maximum differen- tial input voltage to 7.5 v. this is to prevent emitter-base junction breakdown from occurring in the input stage of the op176 when very large differential voltages are applied. however, in order to preserve the op176s low input noise voltage, internal resistances in series with the inputs were not used to limit the current in the clamp diodes. in small signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large transient currents can flow through these diodes. although these diodes have been designed to carry a current of 5 ma, external resistors as shown in figure 30 should be used in the event that the op176s differential voltage were to exceed 7.5 v. figure 30. input overcurrent protection op176 2 3 7 6 5 4 1 p1 ? s v out w p1 = 10k w v os trim range = 2mv +v s op176 1.4k 1.4k + 2 3 6 50hz / 300 mhz \ 0 hz mkr: 5.4 hz 10.0 v /div ch a: 80.0 v fs bw: mkr: 15.9 v/ hz op176 op37 op37 output 4.42k w 909 w 909 w 100 w 490 w 100 w
op176 rev. 0 C10C figure 33. unity gain follower figure 34. unity gain inverter in inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capaci- tance (r s and c s ) and the op176s input capacitance (c in ), as shown in figure 35. with r s and r f in the k w range, this pole can create excess phase shift and even oscillation. a small capacitor, c fb , in parallel with r fb eliminates this problem. by setting r s (c s + c in ) = r fb c fb , the effect of the feedback pole is completely removed. figure 35. compensating the feedback pole output voltage phase reversal since the op176s input stage combines bipolar transistors for low noise and p-channel jfets for high speed performance, the output voltage of the op176 may exhibit phase reversal if either of its inputs exceeds the specified negative common-mode input voltage. this might occur in some applications where a trans- ducer, or a system, fault might apply very large voltages upon the inputs of the op176. even though the input voltage range of the op176 is 10.5 v, an input voltage of approximately C13.5 v will cause output voltage phase reversal. in inverting amplifier configurations, the op176s internal 7.5 v clamping diodes will prevent phase reversal; however, they will not prevent this effect from occurring in noninverting applications. for these applications, the fix is a 3.92 k w resistor in series with the noninverting input of the device and is illustrated in figure 31. figure 31. output voltage phase reversal fix overdrive recovery the overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output level from a saturated condition. this recovery time is impor- tant in applications where the amplifier must recover quickly after a large abnormal transient event. the circuit shown in figure 32 was used to evaluate the op176s overload recovery time. the op176 takes approximately 1 m s to recover to v out = +10 v and approximately 900 ns to recover to v out = C10 v. figure 32. overload recovery time test circuit high speed operation as with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. recommended circuit configurations for inverting and noninverting applications are shown in figure 33 and figure 34. v in r s 909 w v out r l w 2.43k w r2 w 10k w r1 w 1k w 4vp-p @100hz 6 2 3 op176 +15v + 10f 0.1f 2 3 7 6 4 v in v out r l 2k w ?5v 10f 0.1f op176 +15v + 10f 0.1f 2 3 7 6 4 v in v out 2k w ?5v 10f 0.1f op176 10pf 4.99k w 2.49k w 4.99k w + c fb r fb c in v out r s c s w r s 3.92k w w r l 2k w r fb * v in v out *r fb is optional op176 2 3 6
op176 rev. 0 C11C attention to source impedances minimizes distortion since the op176 is a very low distortion amplifier, careful attention should be given to source impedances seen by both inputs. as with many fet-type amplifiers, the p-channel jfets in the op176s input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. in an inverting configuration, the inverting input is held at a virtual ground and, as such, does not vary with input voltage. thus, since the gate-to-source voltage is constant, there is no distor- tion due to input capacitance modulation. in noninverting applications, however, the gate-to-source voltage is not constant. the resulting capacitance modulation can cause distortion above 1 khz if the input impedance is > 2 k w and unbalanced. figure 36 shows some guidelines for maximizing the distortion performance of the op176 in noninverting applications. the best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors (r f and r g ) is less than 2 k w . keeping the values of these resistors small has the added benefits of reducing the thermal noise of the circuit and dc offset errors. if the parallel combina- tion of r f and r g is larger than 2 k w , then an additional resistor, r s , should be used in series with the noninverting input. the value of r s is determined by the parallel combina- tion of r f and r g to maintain the low distortion performance of the op176. for a more generalized treatment on circuit impedances and their effects on circuit distortion, please review the section on active filters at the end of the applications section. driving capacitive loads as with any high speed amplifier, care must be taken when driving capacitive loads. the graph in figure 14 shows the op176s overshoot versus capacitive load. the test circuit is a standard noninverting voltage follower; it is this configuration that places the most demand on an amplifiers stability. for capacitive loads greater than 400 pf, overshoot exceeds 40% and is roughly equivalent to a 45 phase margin. if the applica- tion requires the op176 to drive loads larger than 400 pf, then external compensation should be used. figure 37 shows a simple circuit which uses an in-the-loop compensation technique that allows the op176 to drive any capacitive load. the equations in the figure allow optimization of the output resistor, r x , and the feedback capacitor, c f , for optimal circuit stability. one important note is that the circuit bandwidth is reduced by the feedback capacitor, c f , and is given by: bw = 1 2 p r f c f figure 37. in-the-loop compensation technique for driving capacitive loads applications using the op176 a high speed, low noise differential line driver the circuit of figure 38 is a unique line driver widely used in many applications. with 18 v supplies, this line driver can deliver a differential signal of 30 v p-p into a 2.5 k w load. the high slew rate and wide bandwidth of the op176 combine to yield a full power bandwidth of 130 khz while the low noise front end produces a referred-to-input noise voltage spectral density of 15 nv/ ? hz . the circuit is capable of driving lower impedance loads as well. for example, with a reduced output level of 5 v rms (14 v p-p), the circuit exhibits a full-power bandwidth of 190 khz while driving a differential load of 249 w ! the design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount importance. like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. other circuit gains can be set according to the equation in the diagram. this allows the design to be easily set for noninverting, inverting, or differential operation. figure 38. a high speed, low noise differential line driver 6 2 3 a2 6 3 2 a1 3 2 6 a3 v in v o1 v o2 r3 2k w r9 50 w r11 1k w p1 10k w r12 1k w r10 50 w r8 2k w r2 2k w r5 2k w r4 2k w r1 2k w r7 2k w r6 2k w v o2 ?v o1 = v in a1, a2, a3 = op176 gain = set r2, r4, r5 = r1 and r6, r7, r8 = r3 r3 r1 op176 v in v out r f r g r s * * r s = r g //r f if r g //r f > 2k w for minimum distortion figure 36. balanced input impedance to mininize distortion in noninverting amplifier circuits r x = r o r g r f op176 c f r x c l r g r f v out where r o = open-loop output resistance v in c f = i + ( i | a cl | )( r f + r g r f ) c l r o [ ]
op176 rev. 0 C12C a low noise microphone preamplifier with a phantom power option figure 39 is an example of a circuit that combines the strengths of the ssm2017 and the op176 into a variable gain micro- phone preamplifier with an optional phantom power feature. the ssm2017s strengths lie in its low noise and distortion, and gain flexibility/simplicity. however, rated only for 2 k w or higher loads, this makes driving 600 w loads somewhat limited with the ssm2017 alone. a pair of op176s are used in the circuit as a high current output buffer (u2) and a dc servo stage (u3). the op176s high output current drive capability provides a high level drive into 600 w loads when operating from 18 v supplies. for a complete treatment of the circuit design details, the interested reader should consult application note an-242, available from analog devices. this amplifiers performance is quite good over programmed gain ranges of 2 to 2000. for a typical audio load of 600 w , thd + n at various gains and an output level of 10 v rms is illustrated in figure 40. for all but the very highest gain, the thd + n is consistent and well below 0.01%, while the gain of 2000 becomes more limited by noise. the noise performance of the circuit is exceptional with a referred-to-input noise voltage spectral density of 1 nv/ ? hz at a circuit gain of 1000. 1.0 0.1 0.010 0.001 20 100 1k 10k 20k g = 2000 g = 200 g = 20 g = 4 v s = 18v 80khz lpf figure 40. low noise microphone preamplifier thd + n performance at various gains (v out = 10 v rms and r l = 600 w ) figure 39. a low noise microphone preamplifier + + + + + w r10 100 w +48v r9 6.81k w r8 6.81k w c8 47f/ 63v phantom power supply connections, interlocked with +/? s (see note 5). z1 z2 to microphone ?n +in w r p 1 49.9 w c in 1 47f/ 63v w r p 2 49.9 w c in 2 47f/ 63v common z3 z4 c g 2 2200f/ 10v c g 1 2200f/ 10v r g r b 1 10k w r b 2 10k w c n 4.7nf/ film 1) 3) +v s 3 8 1 2 6 5 4 7 u1 ssm2017p ? s c rf 2 100pf c rf 1 100pf r1 10k w r6 10k w r7 1k w c5 33pf output 6 4 2 3 7 6 2 3 w r3 49.9 w r5 221k w r2 20k w c1 1f film r4 221k w d1 d2 1n458 +v s ? s u2 op176 u3 op176 c2 1f film out common notes: 1) z1?4 1n752 (see text). 2) c inx , c gx low leakage electrolytic types (see text). 3) gain = g = 2 x ((10k/r g ) +1) (see text). 4) all resistors 1% metal film. 5) dotted phantom power related components optional (see text). +v s ? s +18v ?8v c6 0.1f c7 0.1f c3 100f/25v c4 100f/25v + + 1n458 4 7 ? s +v s
op176 rev. 0 C13C a low noise, +5 v/+10 v reference in many high resolution applications, voltage reference noise can be a major contributor to overall system error. monolithic voltage references often exhibit too much wide band noise to be used alone in these systems. only through careful filtering and buffering of these monolithic references can one realize wide- band microvolt noise levels. the circuit illustrated in figure 41 is an example of a low noise precision reference optimized for both ac and dc performance around the op176. with a +10 v reference (the ad587), the circuit exhibits a 1 khz spot output noise spectral density < 10 nv/ ? hz . the reference output voltage is selectable between 5 v and 10 v, depending only on the selection of the monolithic reference. the output table illustrated in the figure provides a selection of monolithic references compatible with this circuit. figure 41. a low noise, +5 v/+10 v reference in operation, the basic reference voltage is set by u1, either a 5 v or 10 v 3-terminal reference chosen from the table. in this case, the reference used is a 10 v buried zener reference, but all u1 ic types shown can plug into the pinout and can be optionally trimmed. the stable 10 v from the reference is then applied to the r1-c1-c2 noise filter, which uses electrolytic capacitors for a low corner frequency. when electrolytic capacitors are used for filtering, one must be cognizant of their dc leakage current errors. here, however, a dc bootstrap of c1 is used, so this capacitor sees only the small r2 dc drop as bias, effectively lowering its leakage current to negligible levels. the resulting low noise, dc-accurate output of the filter is then buffered by a low noise, unity gain op amp using an op176. with the op176s low v os and control of the source resistances, the dc performance of this circuit is quite good and will not compromise voltage reference accuracy and/or drift. also, the op176 has a typical current limit of 50 ma, so it can provide higher output currents when compared to a typical ic reference alone. a differential adc driver high performance audio sigma-delta adcs, such as the stereo 16-bit ad1878 and the 18-bit ad1879, present challenging design problems with regards to input interfacing. because of an internal switched capacitor input circuit, the adc input structure presents a difficult dynamic load to the drive amplifier with fast transient input currents due to their 3 mhz adc sampling rate. also, these adcs inputs are differential with a rated full-scale range of 6.3 v, or about 4.4 v rms. hence, the adc interface circuit of figure 42 is designed to accept a balanced input signal to drive the low dynamic impedances seen at the inputs of these adcs. the circuit uses two op176 figure 42. a balanced driver circuit for sigma-delta adcs amplifiers as inverting low-pass filters for their speed and high output current drive. the outputs of the op176s then drive the differential adc inputs through an rc network. this rc network buffers the amplifiers against step changes at the adc sampling inputs using one differential (c3) and two common- mode connected capacitors (c4 and c5). the 51 w series resistors isolate the op176s from the heavily capacitive loads, while the capacitors absorb the transient currents. operating on 12 v supplies, this circuit exhibits a very low thd + n of 0.001% at 5 v rms outputs. for single-ended drive sources, a third op amp unity gain inverter can be added between r2s (+) input terminal and r4. for best results, short-lead, noninduc- tive capacitors are suggested for c3, c4, and c5 (which are placed close to the adc), and 1% metal-film types for r1 through r6. for surface mount pcbs, these components can be npo ceramic chip capacitors and thin-film chip resistors. c1 100pf r1 5.76k w r2 5.62k w w r5 51 w c2 100pf r3 5.49k w r4 5.62k w w r6 51 w c4 0.01f u1 u2 c3 0.0047f c5 0.01f balanced inputs = ag, pin 10 or 18 v in v in + to ad1878/ ad1879 sigma- delta adc l & r inputs u1, u2 = op176 ?2v analog (+) (? notes c1?5 = npo ceramic, non-inductive, c3-c5 close to adc r1?6 = 1% metal film 0.1f 0.1f 100/25v +12v analog com +v s ? s to u1, u2 100/25v (+) use for single-ended inputs 5k w 5k w output table v out 10v 10v 10v 10v 5v 5v 5v 5v u1 ad587 ref01 ref10 ad581 ref195 ad586 ref02 ref05 tolerance (+/?v) 5 to 10 30 to 100 30 to 50 5 to 30 2 to 10 2.5 to 20 15 to 50 15 to 25 u2 op176 4 7 6 2 3 +15v r1 1k w r3 100 w r2 10k w c4 0.1f c2 100f/25v 6 5 8 4 r trim 10k w c1 100f/25v c3 100f/25v r5 1.1k w r4 100 w r6 3.3 w c5 10f/25v v out ref common (optional) 2 u1
op176 rev. 0 C14C an riaa phono preamp figure 43 illustrates a simple phono preamplifier using riaa equalization. the op176 is used here to provide gain and is chosen for its low input voltage noise and high speed perfor- mance. the feedback equalization network (r1, r2, c1, and c2) forms a three time constant network, providing reasonably accurate equalization with standard component values. the input components terminate a moving magnet phono cartridge as recommended by the manufacturer, the element values shown being typical. when this ac coupled circuit is built with a low noise bipolar input device such as the op176, amplifier bias current makes direct cartridge coupling difficult. this circuit uses input and output capacitor coupling to minimize biasing interactions. input ac coupling to the amplifier is provided via c5, and the low frequency termination resistance, r t , is the parallel equiva- lent of r6 and r7. r3 of the feedback network is ac grounded via c4, a large value electrolytic. additionally, this resistor is set to a low value to minimize circuit noise from nonamplifier sources. these design measures reduce the dc offset at the output of the op176 to a few millivolts. the output coupling network of c3 and r4 is shown as suitable for wide band response, but it can be set to a 7950 m s time constant for use as a 20 hz rumble filter. the 1 khz gain (g) of this circuit, controlled by r3, is calculated as: g (@ 1 khz) = 0.101 1 + r1 r3 for an r3 of 200 w , the circuit gain is just under 50 (? 34 db), and higher gains are possible by decreasing r3. for any value of r3, the r5-c6 time constant should be equal to r3 and the series equivalent of c1 and c2. using readily available standard values for network elements (r1, r2, c1, and c2) makes the design easily reproducible and inexpensive. these components are ideally high quality precision types, for low equalization errors and minimum parasitics. one percent metal-film resistors and two percent film capacitors of polystyrene or polypropylene are recom- mended. using the suggested values, the frequency response relative to the ideal riaa characteristic is within 0.2 db over 20 hzC20 khz. even tighter response can be achieved by using the alternate values, shown in brackets [ ], with the trade-off of a non off-the-shelf part. as previously mentioned, the op176 was chosen for three reasons: (1) for optimal circuit noise performance, the amplifier used should exhibit voltage and current noise densities of 5 nv/ ? hz and 1 pa/ ? hz , respectively. (2) for high gain accuracy, especially at high stage gains, the amplifier should exhibit a gain bandwidth product in excess of 5 mhz. (3) equally important because of the 100% feedback through the network at high frequencies, the amplifier must be unity gain stable. with the op176, the circuit exhibits low distortion over the entire range, generally well below 0.01% at outputs levels of 5 v rms using 18 v supplies. to achieve maximum perfor- mance from this high gain, low level circuit, power supplies should be well regulated and noise free, and care should be taken with shielding and conductor layout. active filter circuits using the op176 a general active filter topology that lends itself to both high-pass (hp) and low-pass (lp) filters is the well known sallen-key (sk) vcvs (voltage-controlled, voltage source) architecture. this filter type uses the op amp as a fixed gain voltage follower at either unity or a higher gain. discussed here are simplified 2- pole, unity gain forms of these filters, which are attractive for several reasons: one, at audio frequencies, using an amplifier with a 10 mhz bandwidth such as the op176, these filters exhibit reasonably low sensitivities for unity gain and high damping (low q). second, as voltage followers, they are also inherently gain accurate within their pass band; hence, no gain resistor scaling errors are generated. third, they can also be made dc accurate, with output dc errors of only a few millivolts. the specific filter response in terms of hp, lp and damping is determined by the rc network around the op amp, as shown in figure 44a. figure 43. an riaa phono preamplifier circuit r6 w 100k w w r7 100k w c t 150pf c5 100 m f/25v moving magnet pickup 3 2 7 6 4 op176 u1 +v s ? s r t = r6 | | r7 ~ 50k w c1 0.03f 2% c2 0.01f 2% r3 w 200 w (34db) w 100 w (40db) c4 1000f/16v c3 100 m f/25v w r5 499 w w r4 100k w c6 3nf v out 0.1f 0.1f +v s ? s 100f 100f +18v ?8v r1 100k w 1% [97.6k w ] r2 8.25k w 1% [7.87k w ]
op176 rev. 0 C15C high pass sections figure 44a illustrates the high-pass form of a 2-pole sk filter using an op176. for simplicity and practicality, capacitors c1 and c2 are set equal (c), and resistors r2 and r1 are adjusted to a ratio, n, which provides the filter damping coefficient, a , as per the design expressions. this high pass design is begun with selection of standard capacitor values for c1 and c2 and a calculation of n. the values for r1 and r2 are then determined from the following expressions: r1 = 1 2 p freq c n and r2 = n r1 figures 44a. two-pole unity gain hp/lp active filters in this examples, circuit a (or 1/q) is set equal to ? 2 , providing a butterworth (maximally flat) characteristic. the filter corner frequency is normalized to 1 khz, with resistor values shown in both rounded and (exact) form. various other 2-pole response shapes are possible with appropriate selection of a , and fre- quency can be easily scaled, using inversely proportional r or c values for a given a . the 22 v/ m s slew rate of the op176 will support 20 v p-p outputs above 100 khz with low distortion. the frequency response resulting with this filter is shown as the dotted hp portion of figure 45. +v s r1 11k (11.254k) c1 0.01f 7 4 6 3 2 out in op176 c2 0.01f ? s r2 22k (22.508k) given: a, freq set c1 = c2 = c a = = 2 n 1 q n = = 4 a 2 r2 r1 r1 = 1 r2 = n x r1 z comp z comp (high pass) in (? r2 output c1 c2 r1 1 khz bw shown 2 p freq x c x n low pass sections in the lp sk arrangement of figure 44b, the r and c elements are interchanged where the resistors are made equal. here, the ratio of c2/c1 (m) is used to set the filter a , as noted. otherwise, this filter is similar to the hp section, and the resulting 1 khz lp response is shown in figure 45. the design begins with a choice of a standard capacitor value for c1 and a calculation of m. this then forces a value of m c1 for c2. then, the value for r1 and r2 (r) is calculated according to the following equation: r = 1 2 p freq c1 m figures 44b. two-pole unity gain hp/lp active filters figure 45. relative frequency response of 2-pole, 1 khz butterworth lp (left) and hp (right) active filters +v s r1 11k (11.254k) c1 0.02f 7 4 6 3 2 out in op176 c2 0.01f ? s r2 11k (11.254k) given: a, freq a = = 2 m 1 q m = = 4 a 2 c2 c1 c2 = m x c1 z comp in (? r2 output c1 c2 r1 1 khz bw shown choose c1 r = 1 2 p freq x c1 x m z comp (low pass) 100 50k 10k 1k 20 10.000 ?0.00 ?0.00 ?0.00 ?0.00 ?0.00 ?0.00 ?0.00 0.0 lp hp frequency ?hz dbr
op176 rev. 0 C16C passive component selection for active filters the passive components suitable for active filters deserve more than casual attention. resistors should be 1%, low tc, metal- film types of the rn55 or rn60 style. capacitors should be 1% or 2% film types preferably, such as polypropylene or polysty- rene, or npo (cog) ceramic for smaller values. active filter circuit subtleties in designing active filter circuits with the op176, moderately low values (10 k w or less) for r1 and r2 can be used to minimize the effects of johnson noise when critical. the practical tradeoff is, of course, capacitor size and expense. dc errors will result for larger values of resistance, unless compen- sation for amplifier input bias current is used. to add bias compensation in the hp filter section of figure 42a, a feedback compensation resistor equal to r2 can be used. this will minimize bias current induced offset to the product of the op176s i os and r2. for an r2 of 25 k w , this produces a typical compensated offset voltage of 50 m v. similar compensation is applied to figure 42b, using a resistance equal to r1+ r2. using dc compensation, filter output dc errors using the op176 will be dominated by its v os , which is typically 1 mv or less. a caveat here is that the additional resistors can increase noise substantially. for example, a 10 k w resistor generates ~ 12 nv/ ? hz of noise and is about twice that of the op176. these resistors can be ac bypassed to eliminate their noise using a simple shunt capacitor chosen such that its reactance (x c ) is much less than r at the lowest frequency of interest. a more subtle form of ac degradation is also possible in these filters, namely nonlinear input capacitance modulation. this issue was previously covered for general cases in the section on minimizing distortion. in active filter circuits, a fully compen- sating network (for both dc and ac performance) can be used to minimize this distortion. to be most effective, this network (z comp ) should include r1 through c2 as noted for either filter type, of the same style and value as their counterparts in the forward path. the effects of a z comp network on the thd + n performance of two 1 khz hp filters is illustrated in figure 46. one filter (a) is the example shown in figure 44a (curves a1 and a2), while the second (b) uses rc values scaled 10 times upward in impedance (curves b1 and b2). both filters operate with a 2 v rms input, 18 v supplies, 100 k w loading, and analyzer bandwidth of 80 khz. figure 46. thd + n (%) vs. frequency for various 1 khz hp active filters illustrating the effects of the z comp network curves a1 and b1 show performance with z comp shorted, while curves a2 and b2 illustrate operation with z comp active. for the a example values, distortion in the pass band of 1 khzC20 khz is below 0.001% compensated, and slightly higher uncompensated. with the higher impedance b net- work, there is a much greater difference between compensated and uncompensated responses, underscoring the sensitivity to higher impedances. although the positive effect of z comp is seen for both a and b cases, there is a buffering effect which takes place with lower impedances. as case a shows, when using larger capacitance values in the source, the amplifiers nonlinear c-v input characteristics have less effect on the signal. thus, to minimize the necessity for the complete z comp com- pensation, effective filter designs should use the lowest capaci- tive impedances practical, with an 0.01 m f lower value limit as a goal for lowest distortion (while lower values can certainly be used, they may suffer higher distortion without the use of full compensation). since most designs are likely to use low relative impedances for reasons of low noise and offset, the effects of cm distortion may or may not actually be apparent to a given application. 20 100 20k 1k 1 0.010 0.0001 0.001 0.1 10 k b1 a1 b2 a2 frequency ?hz thd +n ?%
op176 rev. 0 C17C figure 47. op176 spice model schematic 35 10 11 v n1 v n2 d n1 d n2 12 13 14 v n3 v n4 d n3 d n4 15 16 17 v n5 v n6 d n5 d n6 c n1 c 1 e m r 4 c 2 5 6 q1 q2 3 7 8 9 r 3 36 d2 d1 c in 2 1 ?n +in i os r 5 r 6 4 i 1 e p 97 e n e os 98 98 cm1 cm2 i sy r 15 v 5 d8 g9 r 16 g8 r 17 v 4 d7 r 18 27 g5 r 14 c8 c 9 d6 d5 99 28 30 29 f 1 31 32 33 d10 g7 g6 d9 50 98 f 2 34 l 2 g 1 r 7 21 c 3 v 3 97 51 d 4 20 g 2 r 8 c 4 r 9 23 g 3 r 10 c 5 24 g 4 r 11 c 6 v 2 d 3 19 26 e 2 r 13 25 r 12 c7 98 22 98 e ref
op176 rev. 0 C18C op176 spice model * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output *||||| *||||| .subckt op176 1 2 99 50 34 * * input stage & pole at 100 mhz * r3 5 51 2.487 r4 6 51 2.487 cin 1 2 3.7e-12 cm1 1 98 7.5e-12 cm2 2 98 7.5e-12 c2 5 6 320e-12 i1 97 4 100e-3 ios 1 2 1e-9 eos 9 3 poly(1) (26,28) 0.2e-3 1 q1 5 2 7 qx q2 6 9 8 qx r5 7 4 1.970 r6 8 4 1.970 d1 2 36 dz d2 1 36 dz en 3 1 (10,0) 1 gn1 0 2 (13,0) 1e-3 gn2 0 1 (16,0) 1e-3 * eref 98 0 (28,0) 1 ep 97 0 (99,0) 1 em 51 0 (50,0) 1 * * voltage noise source * dn1 35 10 den dn2 10 11 den vn1 35 0 dc 2 vn2 0 11 dc 2 * * current noise source * dn3 12 13 din dn4 13 14 din vn3 12 0 dc 2 vn4 0 14 dc 2 * * current noise source * dn5 15 16 din dn6 16 17 din vn5 15 0 dc 2 vn6 0 17 dc 2 * * gain stage & dominant pole at 32 hz * r7 18 98 1.243e6 c3 18 98 4e-9 g1 98 18 (5,6) 4.021e-1 v2 97 19 1.35 v3 20 51 1.35 d3 18 19 dx d4 20 18 dx * * pole/zero pair at 1.5 mhz/2.7 mhz * r8 21 98 1e3 r9 21 22 1.25e3 c4 22 98 47.2e-12 g2 98 21 (18,28) 1e-3 * * pole at 100 mhz * r10 23 98 1 c5 23 98 1.59e-9 g3 98 23 (21,28) 1 * * pole at 100 mhz * r11 24 98 1 c6 24 98 1.59e-9 g4 98 24 (23,28) 1 * * common-mode gain network with zero at 1 khz * r12 25 26 1e6 c7 25 26 60e-12 r13 26 98 1 e2 25 98 poly(2) (1,98) (2,98) 0 2.50 2.50 * * pole at 100 mhz * r14 27 98 1 c8 27 98 1.59e-9 g5 98 27 (24,28) 1 * * output stage * r15 28 99 58.333e3 r16 28 50 58.333e3 c9 28 50 1e-6 isy 99 50 1.743e-3 r17 29 99 100 r18 29 50 100 l2 29 34 1e-9 g6 32 50 (27,29) 10e-3 g7 33 50 (29,27) 10e-3 g8 29 99 (99,27) 10e-3 g9 50 29 (27,50) 10e-3 v4 30 29 1.74 v5 29 31 1.74 f1 29 0 v4 1 f2 0 29 v5 1 d5 27 30 dx d6 31 27 dx d7 99 32 dx d8 99 33 dx d9 50 32 dy d10 50 33 dy * * models used * .model qx pnp(bf=5e5) .model dx d(is=1e-12) .model dy d(is=1e-15 bv=50) .model dz d(is=1e-15 bv=7.0) .model den d(is=1e-12 rs=4.35k kf=1.95e-15 af=1) .model din d(is=1e-12 rs=268 kf=1.08e-15 af=1) .ends op176
op176 rev. 0 C19C outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead narrow-body so (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 4 5 1 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80)
C20C printed in u.s.a. c1878C10C1/94
op176 rev. 0 C21C for catalog ordering guide model temperature range package description package option* op176gp C40 c to +85 c 8-pin plastic dip n-8 op176gs C40 c to +85 c 8-pin soic so-8 op176gsr C40 c to +85 c so-8 reel, 2500 pieces op176gbc +25 c dice *for outline information see package information section.

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